(1) Field of the Invention
The invention relates to a method to erase memory cells in a memory device, such as an array of Flash EPROM or EEPROM memory cells. More particularly, the invention relates to a method to erase, erase verify, erase inhibit, and over erase correct, and over erase verify memory cells in a memory device.
(2) Description of the Prior Art
A typical Flash memory device has a memory array comprising a plurality of memory cells arranged in rows (wordlines) and columns (bitlines). Circuits in the device control operations performed on the array, such as erasing, programming, reading, and verification. Each cell in the array comprises some type of floating gate, or adjustable threshold voltage (Vt), device. Typically, the drain of each cell is coupled to a column that is further coupled to a bitline decoder. The source of each cell is coupled to a global source line. The control gate of each cell is coupled to a row that is further coupled to a wordline decoder. The bitline and wordline decoder circuits perform the operations of selecting cells and providing proper voltage biases during the various array operations.
During programming, for instance, a programming voltage, VPP, of typically about 10 Volts is transferred to a selected row, or wordline. At the same time, the column, or bitline is biased to about 5 Volts, while the global source line is biased to about 0 Volts. In this condition, the floating gate of the memory cell will be charged and the threshold voltage, Vt, will be increased. Typically, this translates to a xe2x80x9c0xe2x80x9d state for the cell. Finally, programming operations are typically performed on a bit-by-bit (or cell-by-cell) basis.
Erasing operations are typically performed on blocks of cells within the array, or on the entire array, at one time. To erase the cells, an erasing voltage, sometimes called VNN, is applied to all of the rows, or wordlines, in the block being erased. For example, the VNN voltage may be about xe2x88x9210 Volts. At the same time, about 5 Volts is applied to the global source line. The columns, or bitlines, are left floating. Typically, the wordline and source line voltages are pulsed. During the erasing operation, charge is removed from the floating gate to thereby decrease Vt. The erased state is typically designated the xe2x80x9c1xe2x80x9d state for the cell.
Following the erasing operation, an erase verify is performed to detect any under erased cells that have Vt above the allowable maximum Vt, called Vtmax, for a cell to still be considered erased. For example, Vtmax may have a value of about 1.5 Volts. If an under erased cell is detected, then another erase operation must be performed. However, other erased cells, that were previously not under erased, may become over erased due to the repeated erase pulses. An over erased cell has a Vt that is below an allowable, minimum Vt, called Vtmin, and is typically in the on-state, even with a control gate voltage of about 0 Volts. Over erased cells are not desirable since they conduct and cause bitline leakage. Therefore, the over erased cells can cause erroneous data reads and verification. Further, the over erased cells may overload the bitline power supply during programming or correction.
Referring now to FIG. 1, a prior art Flash memory array is illustrated. A simplified electrical schematic diagram of a column 500 of Flash EEPROM cells 502, 504, 506, and 508, is shown. In this example, one cell 504 is being programmed. Therefore, the control gate of this cell 504 is biased to the programming voltage, VPP. The bitline, BL, is biased to 5 Volts. The global source, VS, is biased to 0 Volts. Meanwhile, the control gates of the other cells 502, 506, and 508, are biased to ground. In this configuration, the expected bitline current, IBL, is equal to I2. None of the other cells, 502, 506, and 508, should contribute any current since each cell should be in the off-state. However, if one or more of the other cells is in an over erased state, then gate voltage of 0 Volts is not sufficient to insure that the cell is OFF since its Vt may be very low, zero, or even negative. Therefore, in the case where all the other cells 502, 506, and 508, are over erased, the bitline current, IBL, is equal to the sum of all the currents, I1, I2, I3, and I4. In a typical Flash EEPROM device, the drains of many of memory transistors cells are connected to each bitline. As many as 512 cells may be connected in to each bitline. The undesirable leakage current may exceed the capability of the power supply from the internal pump circuit during a programming or a correction operation. In the case of many over erased cells in a column, it would be impossible to program or correct the memory cells to the right state. The memory is inoperative.
Referring now to FIG. 2, the prior art Flash memory array is again shown. In this example, memory cell 704 is being checked for an over erase condition. Therefore, the control gates of the other memory cells 702, 706, and 708, are biased to ground. The selected cell 704 is biased to the over erase check voltage. Once again, it is assumed that the grounded-gate devices will not conduct. Therefore, the bitline current, IBL, should equal I2. However, if the non-selected cells are over erased to the point of a very low, or even negative, Vt, then these cells will conduct current. The bitline current, IBL, will then be the sum of all the cell currents. This will cause an erroneous read. It will not be possible to tell if the selected cell 704 is, or is not, over erased. Similarly, the presence of over erased cells can cause an under erase check to give false results.
Referring now to FIG. 3, a prior art over erase detection and correction method is illustrated. However, this method does not address the problems illustrated in FIGS. 2 and 3, and may fail to identify both over erased cells and under erased cells. Because over erased cells may be present during an erase or an erase verify, under erased cells and over erased cells may not be properly identified and may be present after the entire erase method is finished.
Referring now to FIGS. 4A through 4C, another prior art method is shown. In this method, bit-by-bit erase verify, erase, bit-by-bit over erase verify, and over erase correction are performed. According to FIG. 4A, after each erase operation, an erase verify is conducted starting from the first cell 402 and 404 and ending at the last cell 412 and 416. If an under erased bit is detected in step 408, then an erase operation is repeated in step 409. The bit is then erase verified again until it passes. After erase verification of all cells, the method passes to an over erase detection and correction method in FIG. 4B. Again, the verification is performed on all cells, from the first cell 418 and 420 to the last cell 430 and 434. If any over erased bit is detected in step 424, then an over erase correction is performed in step 426. The cell is then over erase verified again. After the over erase verification is performed, the entire array is erase verified again in FIG. 4C. Once again, the method parses the entire array to detect any under erased cells. Even though FIGS. 4A through 4C show an elaborate scheme, the method may not accurately detect all of the under erased or over erased cells. During the verification checks, this method applies ground to the non-selected rows, or wordlines, including those in the erased block. As shown in FIGS. 1 and 2, however, this may not be sufficient to insure that over erased cells do not interfere with the bitline current measurement. As a result, under erased cells may be misidentified as properly erased cells. Further, during an over erase correction, the over erased, non-selected cells on a common bitline with an addressed cell can cause a false over erase detection.
Several prior art inventions describe Flash memory erase, verification, and correction methods. U.S. Pat. No. 5,237,535 to Mielke et al teaches the method to repair over erased cells in a Flash memory as shown in the above-referenced prior art FIG. 3. U.S. Pat. No. 6,122,198 to Haddad et al shows a method to erase, bit-by-bit erase verify, over erase verify, and over erase correct, as shown in above-referenced, FIGS. 4A through 4C.
U.S. Pat. Nos. 5,748,538, 5,848,000, and 5,822,252, all to Lee et al, describe Flash memory architectures and methods of over erase repair. Particularly, U.S. Pat. No. 5,848,000 discloses a flash memory address decoder circuit with a novel latch structure. Three levels of wordline voltages are driven using the unique architecture. Further, U.S. Pat. No. 5,822,252, entitled, xe2x80x9cFlash Memory Wordline Decoder with Over erase Repair,xe2x80x9d issued Oct. 13, 1998, discloses the use of a negative voltage on a non-selected wordline. This patent is assigned to the same assignee as the present invention and is incorporated herein by reference in its entirety.
A principal object of the present invention is to provide an effective method to erase a memory array.
A further object of the present invention is to provide a method to check the erase condition of memory cells of a memory array.
A still further object of the present invention is to provide a method to check the erase condition of erase cells using a novel, three voltage level wordline, or control gate, scheme.
Another still further object of the present invention is to provide a method to check the erase condition where a guaranteed off-state voltage is used to guarantee that even over erased cells are in the off-state during under erase and over erase check.
Another further object of the present invention is to provide a method to verify and correct under erased memory cells in a memory array.
Another still further object of the present invention is to provide a method to verify and correct under erased memory cells where cells are selectively re-erased if an under erase condition is detected.
Another further object of the present invention is to provide a method to detect and correct over erased memory cells in a memory array.
Another still further object of the present invention is to provide a method to detect and correct over erased memory cells where cells are selectively pulsed with a correction voltage if an over erase condition is detected.
In accordance with the objects of the present invention, a method to check the erase condition of memory cells in a memory array device is achieved. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine the erase condition of the selected subsection of the erased section.
Also in accordance with the objects of the present invention, a method to detect and correct an over erase condition in memory cells in a memory array device is achieved. A section of the memory array device is erased to form an erased section and non-erased sections. Subsequent erasing of all subsections of the erased section is enabled. A starting memory address is set to thereby select a subsection of the erased section. Thereafter, under erased memory cells in the selected subsection of the erased section are detected. The detecting comprises, first, forcing control gates of the memory cells in the non-erased sections to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to an under erase check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine the under erase condition of the selected subsection of the erase section, and the subsequent erasing of the selected subsection of the erased section is disabled if the under erase condition does not exist. Thereafter, the memory address is incremented to the next memory address to thereby select a new selected subsection of the erased section. Finally, the steps for detecting under erased memory cells are repeated until every subsection of the erased section is detected. Thereafter, the under erased cell is corrected by erasing the subsections of the erased section wherein the subsequent erasing remains enabled.
Also in accordance with the objects of the present invention, a method to detect and correct an over erase condition in memory cells in a memory array device is achieved. A section of the memory array device is erased to form an erased section and non-erased sections. A starting memory address is set to thereby select a subsection of the erased section. Thereafter, over erased memory cells in the selected subsection of the erased section are detected and corrected. The detecting and correcting comprises, first, forcing control gates of the memory cells in the non-erased sections to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to an over erased check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine the over erase condition of the selected subsection of the erase section, and a correction voltage is pulsed on the control gates of the memory cells of the selected subsection of the erased section if an over erase condition exists. Thereafter, the memory address is incremented to the next memory address to thereby select a new selected subsection of the erased section. Finally, the steps are repeated until every subsection of the erased section is over erase detected and corrected.